Beating the Landauer's limit by trading energy with uncertainty

According to the International Technology Roadmap for Semiconductors in the next 10-15 years the limits imposed by the physics of switch operation will be the major roadblock for future scaling of the CMOS technology. Among these limits the most fundamental is represented by the so-called Shannon-von Neumann-Landauer limit that sets a lower bound to the minimum heat dissipated per bit erasing operation. Here we show that in a nanoscale switch, operated at finite temperature T, this limit can be beaten by trading the dissipated energy with the uncertainty in the distinguishability of switch logic states. We establish a general relation between the minimum required energy and the maximum error rate in the switch operation and briefly discuss the potential applications in the design of future switches. In the last forty years the semiconductor industry has been driven by its ability to scale down the size of the CMOS-FET[2] switches, the building block of present computing devices, and to increase computing capability density up to a point where the power dissipated in heat during computation has become a serious limitation[3, 4]. According to the ITRS[5] the limits imposed by the physics of switch operation will be the roadblock for future scaling in the next 10-15 years. The limit on the minimum energy per switching is set at k B T ln(2) (approx 10 −21 J at room temperature)[6, 7] identified with the so-called Shannon-von Neumann-Landauer[8] (briefly Lan-dauer) limit. Power dissipated versus switching speed of devices have been characterized since the seventies[9, 10] by a linear scaling rule where micro-fabrication capabilities , through the replacement of bipolar transistors with CMOS, allowed the continuation of the exponential increase trend in information processing capability which has been known as Moore's law[11]. However, since 2004 the Nanoelectronics Research Initiative[12], a US based consortium of Semiconductor Industry Association companies , has launched a grand challenge to address the fundamental limits of the physics of switches. Such limits are mainly represented by the minimum energy and minimum time, required to operate a switch and are estimated by assuming that a two-well, one-barrier model is a valid abstraction for electron transport switching devices. In this approach the FET transistor can be thought of as consisting of two wells (source and drain) located at a distance a and separated by a potential energy barrier (channel) of height E b (see Fig.1). The two logic states 0 and 1 are …